From photons
to decisions.
One team builds the whole chain: light from an image sensor processed in an FPGA, carried by embedded Linux, stored in the cloud and turned into the decision of an AI agent. Jugger AI (with its Hukuk, Klinik and Health editions), EuroLingo and JShare are ours; our DO-254 FPGA designs and image-processing IP run in production.
- L6People and companiesJugger Hub: morning briefing, delegation, approval
- L5AI agentsClaude API · privacy vault · tool calling · read-back
- L4CloudFastAPI · SQLite · EU servers · cached prompts
- L3Edge computeNVIDIA Jetson (CUDA/TensorRT) · PetaLinux/Yocto
- L2FPGA IPMIPI CSI-2 → ISP → SDI/HDMI · AXI4-Stream
- L1Silicon and firmwareZynq MPSoC · STM32 · ESP32 · NXP · nRF · bare-metal/RTOS
Three product families, six apps in production. We use every one of them ourselves.
Not showcase apps — products that open every morning: real users, real invoices, real support. Every screenshot below is taken from the live system, nothing is mocked up.
The AI employee that does the work and proves it
Jugger doesn't just answer: it collects quotes, sends e-mail and WhatsApp, reads invoices, produces reports, schedules tasks. Every action passes an approval layer and is read back from the database — no fake "done". In the cloud or on your own server.
Scans all your projects, finds the overdue receivable, the upcoming hearing, the critical stock; say "let Jugger do it" and it takes the task and reports back.
Bookings by voice or photo, VAT, due dates, currencies; drafts the reminder e-mail for an overdue invoice and sends it with your approval.
Requests quotes from dozens of suppliers at once, reads the replies into a comparison table, writes the negotiation e-mail on your behalf.
Kanban, customer and contract tracking, shipments, workflows — one assistant that talks to your projects, no fixed menus to wander through.
Case files, hearings and statutory deadlines computed deterministically; a daily radar on the Official Gazette and case law matched to your files; UYAP-compatible petitions.
For psychologists and psychiatrists: client files, SOAP session notes, PHQ-9/GAD-7 trends, medication and invoicing; names are masked before every AI request.
For coaches and doctors: a library of 876 exercises, programmes and nutrition the AI writes and adjusts weekly, an athlete app, a body map.
Your data is anonymised before it reaches the model. If you prefer, Jugger runs on your own server.
Names, ID and tax numbers, phone numbers and e-mail addresses are replaced by placeholders before the model sees them; they are restored in the reply on the way back to you. The model never sees real identities. For clinic clients and athletes this rule is mandatory.
Our own servers in Germany and Finland; encrypted transport and storage; consent records, data processing agreement (DPA), deletion and portability rights are built into the product. A separate privacy regime for legal and clinical data.
Companies that want it run Jugger AI on their own server or private cloud: data never leaves your premises. One Linux service (FastAPI + SQLite + nginx), an install and update script, your company's own AI API key; with an enterprise licence and maintenance agreement.
Six European languages, an AI teacher in your pocket
Dutch, German, French, Spanish, Italian and English. An AI teacher that understands your level, phoneme-level pronunciation analysis, a conversation coach with real-life scenarios, a full simulation of the Dutch civic-integration exam (inburgering), and "Dutch or Nah?" — a live multiplayer card duel.
- AI teacher, 24/7Grammar, pronunciation, speaking practice — in one chat
- Phoneme-level pronunciationNot "try again" but which sound you got wrong, and why
- InburgeringsexamenReading, listening, writing, speaking and KNM modules
- Live duel30 seconds, a real opponent, weekly leaderboard
Everything everyone shoots, in one album
Wedding, birthday, company event: the guest scans the QR card on the table and uploads without an app or an account, in their own language. Live slideshow on the venue screen, a memory book, photo tasks; one ZIP the next morning. Servers in the EU.
- No app, no accountOpens in the browser; iPhone HEIC included, resumes after a dropped connection
- Automatic in 12 languagesFrom the phone's language: EN, DE, NL, TR, AR, RU, PL, UK…
- Physical productsAcrylic stand, NFC card, table card — printed with your name
- Payment and invoiceCard, iDEAL, Apple Pay, Google Pay; instant PDF invoice
Our image-processing pipeline, in your browser
The pipeline below runs the same algorithms as our FPGA IP, in JavaScript: a synthetic test target is simulated as a Bayer RGGB sensor read-out (colour cast, noise, defective pixels) and then processed stage by stage. Switch stages off and on and see the difference. In the FPGA every block is a line-buffered AXI4-Stream IP with deterministic latency.
IP catalogue
Ready-made, verified, documented blocks. Licensed individually or delivered as the complete pipeline.
| Block | Interface | Format | Function | Latency |
|---|---|---|---|---|
| MIPI CSI-2 RX | D-PHY 1–4 lane · up to 2.5 Gb/s/lane | RAW8 / RAW10 / RAW12 · VC0–3 | Packet decode, lane align, ECC/CRC, virtual channels → AXI4-Stream | — |
| Parallel / LVDS RX | 8–16 bit · HSYNC/VSYNC/DE · SerDes | RAW / YCbCr 4:2:2 | Line/frame framing, clock domain crossing, bit-depth normalise | — |
| BPC | AXI4-Stream · 5×5 window | RAW 8–14 bit | Static map + dynamic hot/dead detection, same-colour median replace | 2 lines |
| Demosaic | AXI4-Stream · 5×5 window | Bayer RGGB/GRBG/GBRG/BGGR → RGB | Edge-directed interpolation, false-colour suppression | 2 lines |
| AWB | AXI4-Stream + AXI-Lite stats | RGB linear | Grey-world / white-patch statistics, per-channel gains, manual override | 0 |
| CCM + Gamma | AXI4-Stream · AXI-Lite coefficients | RGB 3×3 + 1-D LUT | Colour correction matrix, programmable gamma / tone LUT | 0 |
| Enhance | AXI4-Stream · 3×3 / 5×5 | RGB / YCbCr | Noise reduction, unsharp-mask sharpening, local contrast | 1–2 lines |
| Scaler + CSC | AXI4-Stream | RGB ↔ YCbCr 4:4:4 / 4:2:2 | Polyphase scaling, colour-space conversion, letterbox | 2 lines |
| SDI TX | SMPTE 259M / 292M / 424M | SD · HD · 3G-SDI | Scrambler, CRC, line numbering, GTX/GTH transceiver wrapper | — |
| HDMI TX | TMDS · HDMI 1.4b | up to 1080p60 / 4K30 · RGB888 | Infoframes, audio channel, EDID/DDC | — |
| VGA / Parallel TX | RGB888 + syncs · external DAC | up to 1920×1200 | Timing generator (VESA CVT), sync polarity, blanking | — |
From requirement to certificate
FPGA logic, embedded Linux and firmware for aerospace, industrial and medical systems. We actually run the DO-254 / ED-80 process: planning, requirements capture, design, implementation and requirements-based verification on the target hardware — with bidirectional traceability.
DO-254 life cycle (V-model)
Left arm design, right arm verification; every level is matched with its counterpart in the traceability matrix. For DAL A/B, elemental analysis and independent review are added.
Design assurance levels
RTCA DO-254 · EUROCAE ED-80FPGA design
VHDL / SystemVerilog RTL; AMD Zynq-7000, UltraScale+ MPSoC, Versal; Intel Cyclone, Arria, Agilex. Timing closure, high-speed interfaces (LVDS, SerDes, PCIe), DSP ported to fixed-point logic.
Embedded Linux
PetaLinux / Yocto: FSBL, U-Boot, device tree, kernel drivers, rootfs, OTA. Zynq PS–PL bridges, VDMA, the ISP pipeline exposed to Linux through V4L2.
Firmware
Bare-metal and FreeRTOS/Zephyr: STM32 F/H/G, ESP32-S3/C6 (ESP-IDF), NXP i.MX RT / LPC, Nordic nRF52/53/54 (nRF Connect). Bootloaders, secure storage, low power, MISRA C.
Edge AI
CUDA / TensorRT on NVIDIA Jetson Orin: zero-copy from camera pipeline to model, INT8 quantisation, GStreamer/DeepStream integration.
Verification
UVM / cocotb simulation, formal checks, hardware-in-the-loop, measurement reports; the requirement ↔ test traceability matrix is part of the delivery.
Delivery
All sources, testbench, documentation and certification data are yours. Fixed price per phase, maintenance on call.
Platform × capability
What we write on which processor. Filled dot: done in production.
| Platform | RTL / IP | Bare-metal | FreeRTOS / Zephyr | Linux | CUDA / TensorRT | DO-254 |
|---|---|---|---|---|---|---|
| AMD Zynq-7000 / UltraScale+ MPSoC / Versal | ||||||
| Intel Cyclone V / 10 · Arria · Agilex | ||||||
| STM32 F / H / G | ||||||
| ESP32-S3 / C6 (ESP-IDF) | ||||||
| NXP i.MX RT / LPC · i.MX 8 | ||||||
| Nordic nRF52 / 53 / 54 (nRF Connect) | ||||||
| NVIDIA Jetson Orin |
Small team, full stack
MCA Technologies was founded in 2023 in Veldhoven, at the heart of the Brainport region. We combine two disciplines that rarely share a roof: AI products with real users, and hardware-near engineering where mistakes are not an option. The result: software that understands the hardware, hardware that is ready for software.
Timeline
- 2023Veldhoven, NLMCA Technologies founded; FPGA and embedded engineering projects
- 2026 · 04Jugger AI 1.0Jugger AI 1.0 — AI business assistant, first customers
- 2026 · 06EuroLingoEuroLingo in the App Store — 6 European languages, AI teacher
- 2026 · 09Hukuk · Klinik · HealthJugger Hukuk, Klinik and Health; Core v2 intelligence layer, privacy vault
- 2026 · 09Jugger HubJugger Hub: company-level morning briefing and delegation
- Today6 products · 3 languages6 products live, 3 languages, two EU data centres, 176 automated tests on every deploy
Our principles
Tell us about your project
AI product, FPGA design, image processing or firmware — we reply within one business day.